A power-on reset circuit is used in an integrated circuit device to prevent logic circuits in the device from being used when the power supply voltage Vcc is not sufficient for the logic circuits to operate properly. Power-on reset circuits typically include a Vcc detect circuit which detects when Vcc has risen to a level sufficient to operate logic gates in the device. CMOS circuits will begin to operate marginally when Vcc is above the higher of Vtn and Vtp, where Vtn is the threshold voltage of N-channel transistors in the CMOS circuits and Vtp is the threshold voltage of P-channel transistors in the CMOS circuits. But CMOS circuit operation will be more reliable when Vcc is above Vtn+Vtp. To provide a guard band, Vcc detect circuits typically provide a detect signal when Vcc has risen to a higher voltage, for example 2Vtn+Vtp or 2Vtp+Vtn.
FIG. 1 shows a block diagram of such a circuit. In addition to Vcc detect circuit 110, which provides a high output signal at NR10 when Vcc has risen to 2Vtn+Vtp, delay block 120 provides a time delay on the output signal at node NR10. Reset circuit 180 provides an override reset signal in response to an externally provided reset signal. Schmitt trigger circuit 130 has a higher trigger point to rising input signals and a lower trigger point to falling input signals, and thus prevents multiple changes in reset signal on R11 in the event of small variations in the signal on NR10. Buffer 138 converts the R11 signal to the output signal on R12.
In some integrated circuit devices, however, the power-on reset circuit may release the integrated circuit device from the reset mode before all circuits in the device are able to operate properly.